Open Memory Interface (OMI)
IBM's proprietary memory interconnect, replacing direct DDR signaling with a high-speed serial protocol that already powers Power10 and Power11's DDR5 DDIMM memory.
Open Memory Interface (OMI) is IBM's proprietary replacement for direct DDR signaling between processor and memory. Instead of wiring DRAM directly to the CPU over a parallel DDR bus, OMI uses a high-speed serial protocol, letting a single socket support far more memory ports -- IBM's own DDIMM designs support up to 32 DDR5 ports per socket, versus the 8 to 12 a conventional DDR layout allows.
The reliability case is as important as the bandwidth case: because OMI is a managed serial link rather than a raw parallel bus, the system can reroute around a failed lane instead of losing the whole memory channel -- a meaningful reliability, availability, and serviceability (RAS) advantage for enterprise workloads that cannot tolerate memory-related downtime.
OMI already spans two Power generations (Power10 and Power11). IBM's chiplet strategy for the generation after Power11 is described by Bill Starke as enabling "incremental" improvement across future generations rather than ground-up redesign -- which is the strongest available signal that OMI, in some evolved form, carries into Power12. No specific Power12 bandwidth figures have been published.
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