IBM's AI Trajectory: Telum II, Spyre & AIU
How IBM's on-chip AI inference strategy actually connects across the mainframe, Power, and research lines -- and what that implies, without overclaiming, for Power 12.
IBM's AI silicon strategy is not scattered across unrelated products -- it is one research and engineering lineage expressed across three product lines, and tracing that lineage is the most reliable way to reason about where Power12's AI capabilities are headed, without inventing numbers IBM hasn't published.
The lineage, in order
1. IBM Research: the AIU chip family
IBM Research's Artificial Intelligence Unit (AIU) program is the proving ground -- experimental and pre-production AI accelerator silicon that tests ideas before they reach a shipping product.
2. IBM z17: Telum II on-chip accelerator
Telum II puts a native, on-chip AI accelerator into IBM's mainframe processor, delivering 24 TOPS -- four times Telum I's AI throughput -- by executing AI primitives as native instructions instead of routing through memory-mapped I/O.
3. IBM Power11: on-chip Matrix Math Acceleration
Power11 ships its own on-chip AI acceleration for matrix math workloads, and gained Spyre Accelerator compatibility -- IBM's PCIe AI accelerator card -- in December 2025.
4. Stated: "beyond Power11"
IBM Power Processor Chief Architect Bill Starke has said on record that Spyre "will be a piece of the Power11 portfolio and beyond," alongside continued evolution of IBM's WatsonX models -- the clearest available signal that AI acceleration is a permanent, cross-generational commitment for Power, not a Power11-only feature.
What this reasonably implies for Power 12
Given that pattern, it is reasonable to expect Power12 to ship with AI inference acceleration at least as capable as Power11's, likely via an evolved Spyre-class accelerator and/or expanded on-chip matrix acceleration. It is not reasonable to publish a specific TOPS figure, core allocation, or accelerator model number for Power12 -- IBM has not stated one, and Telum II's 24 TOPS figure describes a mainframe chip, not a Power chip.
Every specific number on this page (24 TOPS, 4x Telum I, December 2025 compatibility) is a real, published figure about Telum II or Spyre as they exist today -- not a Power12 projection.