IBM Power 12 Roadmap Intelligence
What Comes After
IBM Power 11
IBM has not announced Power 12. This site tracks what is actually known -- confirmed AI technology building blocks, named engineering leadership, and sourced analyst signals -- and labels everything else as exactly what it is: informed speculation.
Confirmed AI Technology Foundations
Real, shipping IBM AI silicon and interconnect technology that Power 12 is expected to build on -- not invented specs.
IBM Telum II Processor
IBM's mainframe-class processor with a native, on-chip AI accelerator delivering 24 trillion operations per second -- four times the AI throughput of the original Telum chip.
PCIe AI Accelerator CardIBM Spyre Accelerator
IBM's PCIe-based AI accelerator card, built for on-premises generative and traditional AI inference, with confirmed Power11 compatibility arriving December 2025.
AI Research SiliconIBM AIU Chip Family
IBM Research's family of purpose-built AI accelerator chips, the research lineage feeding IBM's production AI silicon strategy across mainframe, Power, and cloud.
Proprietary Memory InterconnectOpen Memory Interface (OMI)
IBM's proprietary memory interconnect, replacing direct DDR signaling with a high-speed serial protocol that already powers Power10 and Power11's DDR5 DDIMM memory.
Open Hardware Standards BodyOpenPOWER Foundation
The IBM-founded, now community-governed foundation that opened the Power ISA to royalty-free licensing, and the institutional structure that any Power12 architecture change has to work within.
Power 12 Roadmap Signals
Every sourced signal about IBM's next Power generation, rated by confidence -- never presented as confirmed specification.
Chiplet Hub-and-Spoke Architecture
IBM's post-Power11 generation is expected to move to a chiplet design -- but with a hub-and-spoke I/O layout instead of the centralized-I/O approach used by AMD.
Samsung Process Node & 2.5D Interposer Speculation
IBM is expected to use a mature Samsung process (5nm or 3nm class) for its post-Power11 chips rather than chasing the industry's bleeding-edge nodes -- a deliberate, stated strategy, not a limitation.
Three-Year Power Release Cadence
Power10 (2021) to Power11 (2025) is a four-year gap, but IBM's broader pattern -- and independent analysis -- points to a roughly three-year cadence going forward, putting a plausible Power12 window around 2027-2028.
IBM i 8.1 Lifecycle Alignment
IBM i 7.6 shipped April 2025; the next major release, IBM i 8.1 (internally referenced as IBM i Next), is projected for 2028 -- the same window analysts expect for Power12, and IBM has historically aligned major IBM i releases with new Power hardware generations.
AI Inference Continuity Signal
IBM has stated on the record that its Spyre-based AI acceleration strategy extends beyond Power11 -- the strongest single data point that Power12 inherits, and likely expands, on-chip and on-node AI inference.
From the Library
Chiplets Are Coming to Power: The Hub-and-Spoke Bet Explained
IBM's own chief architect has confirmed the generation after Power11 moves to chiplets -- and described a design that deliberately doesn't copy AMD's approach.
From Telum II to Power 12: How IBM's AI Silicon Strategy Connects
Telum II, the AIU research chips, and the Spyre Accelerator aren't separate stories -- they're one AI silicon strategy expressed across three IBM product lines.
IBM's Three-Year Power Cadence: What It Tells Us About Power 12 Timing
IBM hasn't announced a Power12 date. But its own release history, tracked closely by independent analysts, points to a fairly narrow window.
Common Questions
Has IBM announced Power 12?
No. "Power 12" is an unofficial, industry-standard placeholder name for the Power generation expected after Power11. IBM has not confirmed the name, a release date, or any specifications. Early evidence of its existence includes GCC compiler patches targeting a post-Power11 processor family, first reported around mid-2025.
When will IBM Power 12 be released?
No date has been announced. Extrapolating IBM's roughly three-year Power/IBM i release cadence from Power11's mid-2025 launch, and cross-referencing the independently projected 2028 date for IBM i 8.1, gives a plausible window of 2027 to 2028 -- but this is an analyst projection, not an IBM commitment.
Will IBM Power 12 use a chiplet design?
IBM Power Processor Chief Architect Bill Starke has confirmed the generation after Power11 is expected to move to a chiplet architecture, with a hub-and-spoke I/O topology (a single I/O hub chiplet surrounded by compute chiplets) rather than a centralized-I/O approach like AMD's. No specific chiplet count, core layout, or product details have been disclosed.
Will Power 12 have on-chip AI acceleration?
This is the most directly confirmed forward-looking AI signal available: IBM Power Processor Chief Architect Bill Starke has stated the Spyre AI Accelerator "will be a piece of the Power11 portfolio and beyond," alongside continued evolution of IBM's WatsonX models. The specific form that takes for the next generation -- expanded on-chip acceleration, a next-generation Spyre card, or otherwise -- has not been disclosed.
Who leads IBM Power Systems engineering?
Bill Starke is IBM's Power Processor Chief Architect and the most consistent public voice on Power's silicon direction. Kris Whitney became IBM i Chief Architect in 2026, succeeding Steve Will after a 41-year IBM career. Jeff Scheel leads Linux for Power architecture, and Yan Zhuo leads IBM i product management.
Why doesn't this site publish Power 12 specs, pricing, or model numbers?
Because IBM has not published any. Publishing invented core counts, clock speeds, or model numbers would misrepresent speculation as fact. This site instead tracks sourced statements, patterns, and analyst projections, each with an explicit confidence label, until IBM makes a real announcement.
Glossary
- AIU (Artificial Intelligence Unit) — IBM Research's family of experimental AI accelerator chips, the upstream research lineage feeding IBM's production AI silicon designs.
- Chiplet Architecture — A processor design approach that splits what was once a single monolithic chip into multiple smaller, interconnected silicon dies (chiplets), often on different manufacturing processes.
- CPW (Commercial Processing Workload) — IBM's proprietary relative performance benchmark for IBM i commercial workloads, used to compare capacity across Power model tiers and generations.
- Hub-and-Spoke I/O — IBM's expected chiplet I/O topology for the post-Power11 generation: a single central I/O hub chiplet surrounded by compute chiplets, rather than centralizing I/O separately from compute.
- IBM i 8.1 (IBM i Next) — The projected next major IBM i operating system release after 7.6, independently projected for 2028 -- the same window analysts expect for Power12.
- Open Memory Interface (OMI) — IBM's proprietary high-speed serial memory interconnect, replacing direct DDR signaling, already used in Power10 and Power11's DDR5 DDIMM memory.
- OpenPOWER Foundation — The IBM-founded (2013), now community-governed foundation that licenses the Power Instruction Set Architecture (ISA) royalty-free to outside implementers.
- Power 10 — IBM's prior-generation Power processor family (S1014, S1022, S1022s, S1024, E1050, E1080), launched in 2021, two generations behind the expected Power12.