IBM Power 12 Roadmap Outlook
IBM has not published a Power 12 specification. Here is what its own engineers, its release history, and independent analysts have actually said -- organized by confidence level, not presented as fact.
"Power 12" is not an official IBM name. It is the placeholder the industry uses for the Power generation that follows Power11, because IBM has not confirmed a name, a release date, or a single specification for it. Everything on this page is sourced to a specific IBM statement or a specific piece of independent analysis, and labeled by how confident that source actually is -- not smoothed into a single narrative.
Why Power11 itself is a clue
Power11 was, by IBM's own description, an evolutionary release: the same core instruction set architecture as Power10, with gains coming from clock speed, core count, DDR5 DDIMM memory, and on-chip AI acceleration rather than a ground-up redesign. IBM Power Processor Chief Architect Bill Starke has said the Power10 core "knocked it out of the park," which is why Power11 built on it rather than replacing it. That framing matters, because it tells you Power11 was never meant to be the architectural leap -- it was banking the current design's remaining headroom before the next real shift.
Signals, ranked by how confirmed they actually are
| Signal | What IBM Has Said or Done | Confidence |
|---|---|---|
| AI acceleration continues past Power11 | Bill Starke, on record: Spyre "will be a piece of the Power11 portfolio and beyond" | High -- direct IBM statement |
| Chiplet architecture for the next generation | Starke has confirmed a chiplet direction and described a hub-and-spoke I/O rationale, without product specifics | High direction, low detail -- IBM-confirmed concept only |
| Conservative process node strategy | Starke: moving 7nm to 5nm "did not provide enough benefit" for the current generation; same evaluation logic expected to apply going forward | Medium -- philosophy confirmed, specific node choice not |
| ~2027-2028 release window | Extrapolated from IBM's roughly three-year Power/IBM i release cadence, and GCC compiler patches already targeting a post-Power11 "future" processor as of mid-2025 | Medium -- pattern-based analyst projection, not an IBM date |
| Samsung 3nm plus 2.5D interposer packaging | Cited by some independent technical analysis as a plausible manufacturing path | Low -- unconfirmed speculation |
What we will not do on this page
We will not publish a model number, a core count, a clock speed, a CPW or rPerf figure, a memory bandwidth number, or a price for Power12. IBM has not published any of those, and any site that shows you one is guessing and not telling you so. When IBM makes an actual Power12 announcement, this page gets rebuilt around real specifications -- until then, it stays a roadmap-signal tracker.
See the full source list and structured entries for each signal in the Directory > Roadmap Signals section, and the confirmed AI silicon building blocks in Directory > AI Technology Foundations.