Glossary

IBM Power 12 Glossary

Terminology for IBM Power hardware, AI acceleration silicon, and the engineering concepts behind IBM's next Power generation.

A

• AIU (Artificial Intelligence Unit) — IBM Research's family of experimental AI accelerator chips, the upstream research lineage feeding IBM's production AI silicon designs.

C

• Chiplet Architecture — A processor design approach that splits what was once a single monolithic chip into multiple smaller, interconnected silicon dies (chiplets), often on different manufacturing processes.
• CPW (Commercial Processing Workload) — IBM's proprietary relative performance benchmark for IBM i commercial workloads, used to compare capacity across Power model tiers and generations.

H

• Hub-and-Spoke I/O — IBM's expected chiplet I/O topology for the post-Power11 generation: a single central I/O hub chiplet surrounded by compute chiplets, rather than centralizing I/O separately from compute.

I

• IBM i 8.1 (IBM i Next) — The projected next major IBM i operating system release after 7.6, independently projected for 2028 -- the same window analysts expect for Power12.

O

• Open Memory Interface (OMI) — IBM's proprietary high-speed serial memory interconnect, replacing direct DDR signaling, already used in Power10 and Power11's DDR5 DDIMM memory.
• OpenPOWER Foundation — The IBM-founded (2013), now community-governed foundation that licenses the Power Instruction Set Architecture (ISA) royalty-free to outside implementers.

P

• Power 10 — IBM's prior-generation Power processor family (S1014, S1022, S1022s, S1024, E1050, E1080), launched in 2021, two generations behind the expected Power12.
• Power 11 — IBM's current, shipping Power processor and server generation, announced July 2025, spanning the entry S1112 through the flagship E1180.
• Power 12 — The unofficial, widely used placeholder name for IBM's Power processor and server generation expected after Power11. IBM has not confirmed this name, a release date, or any specifications.
• Power ISA — The reduced instruction set computer (RISC) architecture underlying every IBM Power processor generation, developed under OpenPOWER Foundation governance.

R

• RAS (Reliability, Availability, Serviceability) — The engineering discipline, central to every IBM Power generation, of designing hardware that minimizes downtime and data loss for mission-critical enterprise workloads.
• rPerf (Relative Performance) — IBM's relative performance metric for AIX and Linux workloads on Power hardware, the AIX/Linux counterpart to the IBM i-focused CPW metric.

S

• Spyre Accelerator — IBM's PCIe-form-factor AI accelerator card for on-premises generative and traditional AI inference, with confirmed Power11 compatibility from December 2025.

T

• Telum II — IBM's second-generation, AI-integrated mainframe processor, powering the z17 system, with an on-chip AI accelerator delivering 24 TOPS.

W

• WatsonX — IBM's enterprise AI and data platform, referenced by IBM's own Power chief architect as continuing to evolve alongside Spyre-based AI acceleration hardware.