IBM Power 12 FAQ

No. "Power 12" is an unofficial, industry-standard placeholder name for the Power generation expected after Power11. IBM has not confirmed the name, a release date, or any specifications. Early evidence of its existence includes GCC compiler patches targeting a post-Power11 processor family, first reported around mid-2025.

No date has been announced. Extrapolating IBM's roughly three-year Power/IBM i release cadence from Power11's mid-2025 launch, and cross-referencing the independently projected 2028 date for IBM i 8.1, gives a plausible window of 2027 to 2028 -- but this is an analyst projection, not an IBM commitment.

IBM Power Processor Chief Architect Bill Starke has confirmed the generation after Power11 is expected to move to a chiplet architecture, with a hub-and-spoke I/O topology (a single I/O hub chiplet surrounded by compute chiplets) rather than a centralized-I/O approach like AMD's. No specific chiplet count, core layout, or product details have been disclosed.

Not confirmed. IBM has stated it evaluates process jumps by delivered customer benefit rather than chasing the industry's most advanced nodes -- it skipped 5nm for the current generation because the jump "did not provide enough benefit." Some independent analysis speculates a mature 5nm or 3nm Samsung process, possibly with 2.5D interposer packaging, but this specific detail is unconfirmed.

This is the most directly confirmed forward-looking AI signal available: IBM Power Processor Chief Architect Bill Starke has stated the Spyre AI Accelerator "will be a piece of the Power11 portfolio and beyond," alongside continued evolution of IBM's WatsonX models. The specific form that takes for the next generation -- expanded on-chip acceleration, a next-generation Spyre card, or otherwise -- has not been disclosed.

There is no Power12-specific IBM statement on this, but IBM's consistent, decades-long philosophy has preserved software compatibility for IBM i and AIX workloads across every prior Power generation, including the Power10-to-Power11 transition. No sourced signal suggests that pattern breaks for Power12.

Telum II is a mainframe processor (powering IBM's z17 system), not a Power chip, and IBM has not stated Power12 uses Telum II silicon. It matters here because it's the clearest public evidence of IBM's on-chip AI inference strategy, which has already extended into the Power line via the Spyre Accelerator's confirmed Power11 compatibility.

Bill Starke is IBM's Power Processor Chief Architect and the most consistent public voice on Power's silicon direction. Kris Whitney became IBM i Chief Architect in 2026, succeeding Steve Will after a 41-year IBM career. Jeff Scheel leads Linux for Power architecture, and Yan Zhuo leads IBM i product management.

Because IBM has not published any. Publishing invented core counts, clock speeds, or model numbers would misrepresent speculation as fact. This site instead tracks sourced statements, patterns, and analyst projections, each with an explicit confidence label, until IBM makes a real announcement.

This site's sibling, power11.as400system.com, is the full specification authority for the current, shipping Power11 generation -- every model, processor option, memory and storage configuration, and sourcing vendor.

Any change IBM makes to the Power instruction set architecture -- including a chiplet transition -- happens within the governance and royalty-free licensing structure the OpenPOWER Foundation maintains. The Foundation itself doesn't set IBM's product roadmap, but it is the institutional backdrop for IBM's stated commitment to ISA continuity and controlled openness across generations.