IBM Power 12 CPU
What is actually known about IBM's next Power processor: chiplet packaging, process node strategy, on-die AI acceleration, and the memory interface ... each ranked by how confirmed the source really is.
There is no Power 12 CPU specification, because IBM has not announced a Power 12 processor. It has not confirmed the name, the launch date, the core count, the clock speed, or the process node. What IBM has done is put its Power processor chief architect on the record about design direction several times, and those statements plus the platform's own release history are enough to say something useful. Everything below is sourced and labelled by how confident the source actually is.
If you have arrived here looking for a Power 12 spec sheet to compare against a quote, there is not one to find. What exists today is Power 11, and its processor options are fully published. The useful question at this point is not what Power 12 will be, it is whether anything known about it should change a Power 11 decision you are making now.
What is known about the next Power CPU, by confidence level
Processor signals ranked by how confirmed they are
| Processor question | What IBM has actually said or done | Confidence |
|---|---|---|
| Will it use chiplets? | Bill Starke, IBM Power Processor Chief Architect, has confirmed a chiplet direction and described a hub-and-spoke I/O layout rather than the centralized-I/O approach AMD uses. No product specifics given. | High on direction, none on detail |
| Will AI acceleration continue on the processor? | Starke, on record: Spyre "will be a piece of the Power 11 portfolio and beyond." IBM has also shipped native on-chip AI instructions on Telum II at 24 TOPS. | High ... direct IBM statement |
| What process node? | Starke has said moving 7 nm to 5 nm "did not provide enough benefit" for the current generation. Independent analysis expects a mature Samsung 5 nm or 3 nm class process rather than a bleeding-edge node. | Medium on philosophy, low on the specific node |
| Will it keep the Open Memory Interface? | OMI already carries Power 10 DDR4 and DDR5 DDIMM and Power 11 DDR5 DDIMM, supporting up to 32 DDR5 ports per socket against 8 to 12 with conventional wiring. No statement that it changes. | Medium ... continuity inference, not a commitment |
| When? | Extrapolated from IBM's roughly three-year Power cadence, plus GCC compiler patches already targeting a post-Power 11 "future" processor as of mid-2025. Power 10 to Power 11 was actually four years. | Medium ... pattern-based projection, not an IBM date |
| Core count, clock speed, cache, SMT depth? | Nothing. IBM has published no figure for any of these. | None |
The gap between the first two rows and the last one is the whole story. IBM has been unusually open about architectural direction and completely silent on specification, which is consistent with a processor that is designed but not announced.
The chiplet question is the real architectural change
Power 11 was, by IBM's own framing, an evolutionary release: the same core design as Power 10, with gains taken from clock speed, core count, DDR5 DDIMM memory and on-chip AI acceleration. Starke has said the Power 10 core "knocked it out of the park," which is why Power 11 built on it rather than replacing it. That tells you Power 11 was banking the current design's remaining headroom, and that the next generation is where the structural change lands.
Why hub-and-spoke matters
AMD's chiplet designs centralise I/O in a single die that every compute chiplet talks through. IBM has described a hub-and-spoke layout instead. If that holds, it changes how memory and I/O bandwidth scale with socket count, which is exactly the dimension that has always separated Power enterprise systems from commodity x86.
Why the node choice is deliberate
IBM evaluating 5 nm and declining it is not a manufacturing limitation, it is a stated position: take the node when it pays for itself, not when the marketing calendar says so. Expect the same evaluation applied to the next generation rather than a race to the smallest available process.
What this should and should not change in a decision you are making now
It should not delay a Power 11 purchase
A projected 2027 to 2028 window that is not an IBM date is not a reason to run current hardware past its useful life. If the business case for Power 11 is sound today, waiting for an unannounced processor costs you real capacity and support coverage for a hypothetical gain.
It should shape how you buy AI capability
The one high-confidence statement is that Spyre continues past Power 11. If AI inference is on your roadmap, that argues for a Power 11 configuration with the PCIe capacity to take an accelerator, rather than trying to solve it in the processor specification.
It should inform lease and refresh timing
If you are setting a refresh cycle now, a plausible 2027 to 2028 window is worth knowing when you choose between a three-year and a five-year commitment. That is planning input, not a purchase trigger.
It should not be treated as specification
Nothing on this page is a figure you can put in a sizing exercise or a budget line. Treat every row above as what it is labelled: a direction, an inference, or a projection.
Where the rest of the analysis lives
The full roadmap picture, including everything outside the processor itself, is on the Power 12 roadmap outlook. For the generational comparison, see Power 11 vs Power 12 outlook. The AI acceleration story that carries the highest-confidence signal is covered in the AI trajectory: Telum II, Spyre and AIU, and the design philosophy behind the node and packaging choices is on vertical integration and OpenPOWER philosophy and engineering leadership. If you are making a decision against this timeline, start at planning for the Power 12 transition.