Power 11 vs Power 12 Outlook
Power11 is shipping and fully specified. Power12 is not. Here is what changes IBM confirmed for Power11, set next to what's known -- and not known -- about the generation after it.
This is not a spec-for-spec comparison table, because Power12 does not have published specs. It is a dimension-by-dimension comparison of what IBM has confirmed for Power11 against what is actually known -- confirmed, stated, or projected -- about the generation after it, with an honest confidence rating attached to every Power12 entry.
Dimension-by-dimension outlook
Power 12 entries are sourced statements, patterns, or analyst projections -- never invented specifications.
| Dimension | IBM Power 11 (Confirmed) | IBM Power 12 Outlook | Confidence |
|---|---|---|---|
| Release status | Announced July 2025; shipping | Not announced. "Power 12" is an industry placeholder name, unconfirmed by IBM. | N/A |
| Expected timing | Delivered Q3 2025 | ~2027-2028, extrapolated from IBM's roughly three-year Power/IBM i release cadence | Pattern-based, unconfirmed |
| Core architecture | Same instruction set architecture (ISA) as Power10; evolutionary generation, not a redesign | Expected shift to a chiplet design with a hub-and-spoke I/O layout (one I/O hub chiplet, surrounded by compute chiplets) | IBM-confirmed direction, no product details |
| Process node | Continuity process from Power10; IBM stated the 7nm-to-5nm jump "did not provide enough benefit" to pursue for this generation | Mature 5nm or 3nm Samsung process expected, possibly with 2.5D interposer packaging | Node philosophy confirmed; specific node and packaging are analyst speculation |
| AI acceleration | On-chip Matrix Math Acceleration; Spyre Accelerator (PCIe card) compatibility confirmed for December 2025 | Continued and likely expanded AI acceleration -- Bill Starke: Spyre "will be a piece of the Power11 portfolio and beyond" | Direct IBM statement; scope unconfirmed |
| Memory architecture | DDR5 DDIMM over Open Memory Interface (OMI); up to 32 DDR5 ports per socket | OMI expected to continue given IBM's stated incremental-improvement chiplet strategy; no bandwidth or capacity figures published | Pattern-based, unconfirmed |
| Software / ISA compatibility | Existing IBM i and AIX workloads run unchanged from Power10 | IBM's consistent, decades-long philosophy is cross-generation binary compatibility; no sourced signal suggests a break from that pattern | Philosophy-based; high likelihood, not Power12-specific confirmation |
| Management console (HMC) | Requires HMC v11 (7063-CR2 hardware or vHMC virtual appliance) | Not addressed in any public IBM statement found for this site | Unknown -- no source |
What Else Is Worth Knowing
- IBM has shipped chiplet implementations of the Power line before (Starke: "since way back in 2005"), so a return to chiplets is a known approach, not an unprecedented architectural gamble.
- IBM's chiplet strategy is explicitly framed as enabling incremental, generation-over-generation improvement without full-system redesign -- which is why several Power11 subsystems (OMI, ISA, RAS philosophy) are reasonably expected to carry forward even without specific Power12 confirmation.
- The clearest documented difference from a competitor's chiplet approach (AMD) is IBM's hub-and-spoke I/O topology versus AMD's centralized-I/O, disaggregated-compute model -- driven by IBM's need to minimize latency across very large, multi-socket enterprise configurations.
Sources: https://www.itjungle.com/2024/11/13/ibm-raises-the-curtain-a-little-on-future-power-processors/, https://www.itjungle.com/2025/04/08/plotting-out-power-systems-and-ibm-i-to-2040-and-beyond/, https://chipsandcheese.com/p/ibm-power-whats-next, https://www.itjungle.com/2025/04/14/z17-mainframes-give-ibm-time-to-ramp-ai-accelerated-power11-systems/