Chiplet Hub-and-Spoke Architecture
IBM's post-Power11 generation is expected to move to a chiplet design -- but with a hub-and-spoke I/O layout instead of the centralized-I/O approach used by AMD.
Power11 keeps the same core instruction set architecture (ISA) as Power10, prioritizing clock speed and core count gains -- what IBM Power Processor Chief Architect Bill Starke calls an evolutionary, not revolutionary, generation, because "the core knocked it out of the park."
The generation after Power11 is where IBM has signaled real architectural change: a move to chiplets, similar in concept to AMD's approach, driven by the same physics constraints (the slowing of Moore's Law) that pushed most of the industry toward chiplets already. IBM has shipped chiplet implementations of the Power line before -- Starke notes IBM has "been shipping chiplet implementations of the Power line since way back in 2005" -- so this is a return to a known approach, not an unprecedented gamble.
The hub-and-spoke difference
Where IBM's design is expected to differ from AMD's centralized-I/O, disaggregated-compute model is the I/O topology: a single I/O hub chiplet surrounded by compute chiplets, rather than I/O centralized separately from compute. Starke frames this as optimizing "the connectivity across all sockets" and minimizing latency across large enterprise configurations -- a design constraint that matters enormously for IBM's largest systems, which scale up to 16 sockets.
IBM has confirmed the general chiplet direction and the hub-and-spoke rationale through public engineer commentary. No core counts, clock speeds, socket counts, or model numbers for the next generation have been published.
Related
Samsung Process Node & 2.5D Interposer Speculation
IBM is expected to use a mature Samsung process (5nm or 3nm class) for its post-Power11 chips rather than chasing the industry's bleeding-edge nodes -- a deliberate, stated strategy, not a limitation.
Three-Year Power Release Cadence
Power10 (2021) to Power11 (2025) is a four-year gap, but IBM's broader pattern -- and independent analysis -- points to a roughly three-year cadence going forward, putting a plausible Power12 window around 2027-2028.
IBM i 8.1 Lifecycle Alignment
IBM i 7.6 shipped April 2025; the next major release, IBM i 8.1 (internally referenced as IBM i Next), is projected for 2028 -- the same window analysts expect for Power12, and IBM has historically aligned major IBM i releases with new Power hardware generations.
AI Inference Continuity Signal
IBM has stated on the record that its Spyre-based AI acceleration strategy extends beyond Power11 -- the strongest single data point that Power12 inherits, and likely expands, on-chip and on-node AI inference.
Frequently Asked
Will IBM Power 12 use a chiplet design?
IBM Power Processor Chief Architect Bill Starke has confirmed the generation after Power11 is expected to move to a chiplet architecture, with a hub-and-spoke I/O topology (a single I/O hub chiplet surrounded by compute chiplets) rather than a centralized-I/O approach like AMD's. No specific chiplet count, core layout, or product details have been disclosed.