Chiplet Architecture
A processor design approach that splits what was once a single monolithic chip into multiple smaller, interconnected silicon dies (chiplets), often on different manufacturing processes.
IBM has confirmed a chiplet direction for the Power generation after Power11, following industry-wide adoption of the approach (notably by AMD) as a response to slowing gains from Moore's Law. IBM previously shipped chiplet-based Power designs as early as 2005, making this a return to a known approach rather than an unprecedented shift. See Hub-and-Spoke I/O for how IBM's expected implementation differs from competitors'.
Related Terms
Power 12
The unofficial, widely used placeholder name for IBM's Power processor and server generation expected after Power11. IBM has not confirmed this name, a release date, or any specifications.
Hub-and-Spoke I/O
IBM's expected chiplet I/O topology for the post-Power11 generation: a single central I/O hub chiplet surrounded by compute chiplets, rather than centralizing I/O separately from compute.