Hub-and-Spoke I/O
IBM's expected chiplet I/O topology for the post-Power11 generation: a single central I/O hub chiplet surrounded by compute chiplets, rather than centralizing I/O separately from compute.
IBM Power Processor Chief Architect Bill Starke has described this hub-and-spoke design as optimizing connectivity across all sockets and minimizing latency in IBM's largest enterprise configurations, which scale up to 16 sockets -- a deliberate contrast to AMD's centralized-I/O, disaggregated-compute chiplet model.
Related Terms
Chiplet Architecture
A processor design approach that splits what was once a single monolithic chip into multiple smaller, interconnected silicon dies (chiplets), often on different manufacturing processes.
Power 12
The unofficial, widely used placeholder name for IBM's Power processor and server generation expected after Power11. IBM has not confirmed this name, a release date, or any specifications.