From Telum II to Power 12: How IBM's AI Silicon Strategy Connects

It is tempting to treat IBM's AI chip announcements as a scattered product list: a mainframe processor here, a research chip there, an accelerator card somewhere else. Read closely, they're one lineage.

The research-to-product pipeline

IBM Research's AIU (Artificial Intelligence Unit) chip family is where ideas get proven out before they reach a shipping product. Telum II, the on-chip AI accelerator inside IBM's z17 mainframe processor, is where those ideas become production silicon ... delivering 24 trillion operations per second (TOPS), four times the AI throughput of the original Telum chip, by executing matrix multiplications as native processor instructions rather than routing through memory-mapped I/O.

Power 11 carries the same strategic thread onto IBM's enterprise server line: on-chip Matrix Math Acceleration built into the processor itself, plus December 2025 compatibility with the Spyre Accelerator, IBM's PCIe-card AI accelerator for on-premises generative and traditional AI inference.

The statement that matters most

Of everything IBM has said about AI silicon and Power, one line from Bill Starke is the most directly useful for anyone trying to reason about Power 12: Spyre "will be a piece of the Power 11 portfolio and beyond," alongside continued evolution of IBM's WatsonX models. That is not analyst inference ... it is IBM's own chief architect stating, on the record, that AI acceleration is a permanent commitment across Power generations, not a Power 11-only feature.

What that does and does not tell you

It is reasonable to expect Power 12 ships with AI inference acceleration at least as capable as Power 11's. It is not reasonable to assume Power 12 inherits Telum II's specific 24-TOPS figure ... that number describes a mainframe chip built for a different workload profile, not a stated Power 12 spec.