Chiplets Are Coming to Power: The Hub-and-Spoke Bet Explained

Power11 was, by design, not the architecturally ambitious generation. IBM Power Processor Chief Architect Bill Starke has said Power10's core "knocked it out of the park," which is why Power11 kept the same instruction set architecture and pushed gains through clock speed, core count, memory, and AI acceleration instead. That framing was itself a signal: IBM was banking the current design's remaining headroom, which usually means the real architectural shift is queued up for the following generation.

Why chiplets, and why now

Moore's Law's slowdown has pushed most of the processor industry toward chiplets -- splitting what used to be a single monolithic die into multiple smaller, interconnected pieces of silicon, often built on different, cost-optimized manufacturing processes. AMD has built its entire modern product line around this approach. IBM has confirmed the generation after Power11 follows the same broad direction -- though notably, this isn't new territory for IBM: Starke points out IBM has "been shipping chiplet implementations of the Power line since way back in 2005."

The part that's genuinely different: hub-and-spoke

Where IBM's approach is expected to diverge from AMD's is the I/O topology. AMD centralizes I/O in a separate chiplet, disaggregated from compute. IBM's expected design instead uses a hub-and-spoke layout: one central I/O hub chiplet, with compute chiplets arranged around it. Starke explains the rationale in terms of connectivity: this layout optimizes "the connectivity across all sockets" and minimizes latency -- a constraint that matters enormously more for IBM than for a typical AMD customer, because IBM's largest enterprise Power systems scale up to 16 sockets in a single system, a scale most competing architectures never have to address.